1. Field of the Invention
The present invention relates to a pillar-shaped semiconductor memory device which is a memory device formed in a pillar-shaped semiconductor, and a method for producing the device.
2. Description of the Related Art
In recent years, electronic devices using a memory device typified by a flash memory have been used in various fields, and the market size and application fields of the devices have been further expanding. With these circumstances, the realization of highly integrated memory devices and a reduction in the cost of the memory devices have been desired.
NAND-type flash memories (refer to, for example, C. Y. Ting, V. J. Vivalda, and H. G. Schaefer: “Study of planarized sputter-deposited SiO2”, J. Vac. Sci. Technol. 15(3), p.p. 1105-1112, May/June (1978)) are advantageous in the realization of highly integrated devices and a reduction in the cost of the devices. Vertical NAND-type flash memories in which a plurality of memory cell-transistors are stacked around a semiconductor silicon pillar (hereinafter, a semiconductor silicon pillar is referred to as “Si pillar”) realize more highly integrated devices (refer to, for example, Japanese Unexamined Patent Application Publication No. 4-79369).
FIG. 8 illustrates a sectional structure of an example of a vertical NAND-type flash memory in the related art (refer to, Japanese Unexamined Patent Application Publication No. 4-79369). Silicon (Si) pillars 101a and 101b are formed on an intrinsic semiconductor silicon substrate 100 (hereinafter, an intrinsic semiconductor silicon substrate is referred to as “i-layer substrate”). Silicon dioxide (SiO2) layers 102a and 102b which are tunnel insulating layers are formed so as to surround outer peripheries of the Si pillars 101a and 101b, respectively. Floating electrodes 103a and 103b that electrically float are formed so as to surround outer peripheries of the SiO2 layers 102a and 102b, respectively. Source-side selection gate electrodes 104a and 104b are formed around lower portions of the Si pillars 101a and 101b, respectively. Drain-side selection gate electrodes 105a and 105b are formed around upper portions of the Si pillars 101a and 101b, respectively. Interlayer SiO2 layers 107a and 107b are formed so as to surround outer peripheries of the floating electrodes 103a and 103b, respectively. Word-line electrodes 108a and 108b are formed so as to surround outer peripheries of the interlayer SiO2 layers 107a and 107b, respectively. A common source N+ layer 109 (hereinafter, a semiconductor layer containing a donor impurity in a large amount is referred to as “N+ layer”) is formed in a surface layer of the i-layer substrate 100, the surface layer being connected to bottom portions of the Si pillars 101a and 101b. Drain N+ layers 110a and 110b are formed in top portions of the Si pillars 101a and 101b, respectively. A SiO2 layer 111 is further formed by chemical vapor deposition (CVD) so as to cover the whole. Bit-line wiring metal layers 113a and 113b are respectively formed through contact holes 112a and 112b formed on the drain N+ layers 110a and 110b. Furthermore, P− layers 114a and 114b (hereinafter, a semiconductor layer containing an acceptor impurity in a small amount is referred to as “P− layer”) are respectively formed in the Si pillars 101a and 101 b on the i-layer substrate 100. Memory cell-transistors Qc1 including the SiO2 layers 102a and 102b, the floating electrodes 103a and 103b, the interlayer SiO2 layers 107a and 107b, and the word-line electrodes 108a and 108b are respectively formed on the source-side selection gate electrodes 104a and 104b of the Si pillars 101a and 101b so as to surround outer peripheries of the P− layers 114a and 114b. Memory cell-transistors Qc2 and Qc3 that have the same structure as the memory cell-transistor Qc1 and that are electrically separated from each other are formed on the memory cell-transistor Qc1. Furthermore, source-side selection transistors Qs1 having the source-side selection gate electrodes 104a and 104b are formed below the memory cell-transistors Qc1, Qc2, and Qc3. Drain-side selection transistors Qs2 having the drain-side selection gate electrodes 105a and 105b are formed above the memory cell-transistors Qc1, Qc2, and Qc3. With this structure, a vertical NAND-type flash memory element having a high density is formed.
In the vertical NAND-type flash memory element illustrated in FIG. 8, it is desirable to easily form the SiO2 layers 102a and 102b which are tunnel insulating layers, the interlayer SiO2 layers 107a and 107b, the source-side selection gate electrodes 104a and 104b, the drain-side selection gate electrodes 105a and 105b, the floating electrodes 103a and 103b, and the word-line electrodes 108a and 108b, all of which have less defects and high reliability so as to surround outer peripheral portions of the Si pillars 101a and 101b, respectively.
A known vertical NAND-type flash memory is produced by repeatedly stacking word-line electrode material layers and insulation films in a vertical direction, subsequently forming a through-hole passing through the stacked word-line electrode material layers and the insulation films, subsequently forming an interlayer insulation film, a Si3N4 layer (silicon nitride layer) that stores data charges, and a tunnel SiO2 layer on a surface layer of a side face of the through-hole, and further filling the through-hole with a poly-Si layer (hereinafter, a polycrystalline Si layer is referred to as “poly-Si layer”) which is to become a channel (refer to, for example, the specification of U. S. Patent Application Publication No. 2007/0252201). Also in this vertical NAND-type flash memory, it is desirable to easily form the interlayer insulation film, the Si3N4 layer, the tunnel SiO2 layer, and the word-line electrodes, all of which have less defects and high reliability.
In the vertical NAND-type flash memory illustrated in FIG. 8, it is desirable to easily form the SiO2 layers 102a and 102b, the interlayer SiO2 layers 107a and 107b, the source-side selection gate electrodes 104a and 104b, the drain-side selection gate electrodes 105a and 105b, the floating electrodes 103a and 103b, and the word-line electrodes 108a and 108b, all of which have less defects and high reliability so as to surround outer peripheral portions of the Si pillars 101a and 101b. 